1. Field of the Invention
The present invention relates to design support of integrated circuits, such as FPGAs (field programmable gate arrays), and more particularly, to an integrated circuit design support apparatus having an interface environment for designing integrated circuits such as FPGAs, an integrated circuit design support method, an integrated circuit design support program, and a recording medium.
2. Description of the Related Art
As is well known, FPGAs are integrated circuits to which circuit information within a device can be electrically written by a program externally provided and achieve predetermined circuit functions based on the circuit information. Because of their abilities of reducing process steps, facilitating processes from design to manufacture, and externally changing logics, products designed based on FPGAs are becoming the mainstream in the current circuit design. The designing of FPGAs involve processes, such as management of data regarding the FPGAs and creation of libraries, and the created libraries must be compared with pin names in logic design.
In connection with such design support technology for FPGAs, Japanese Unexamined Patent Application Publication No. 11-110435 discloses a design support system. This design support system uses auxiliary data to which reference is made for the data processing, in addition to design data that are inputs and outputs for data processing included in the design flow. The design support system performs processing using a data process selection table in which design data and auxiliary data are associated for each data processing and are shown in a multilevel hierarchy.
Japanese Unexamined Patent Application Publication No. 8-44782 discloses a design data management apparatus. This management apparatus creates information on a reference/dependence relationship between a library and design data in accordance with contents of library items and uses the information to achieve coherence with the design data, thereby reducing an unwanted operation for retaining the coherence. From input change information, the design data management apparatus extracts a reference design-data identifier that directly refers to the changed item, and selects and outputs the identifier of design data to be updated, based on the reference design-data identifier and the changed information.
Japanese Unexamined Patent Application Publication No. 2002-230052 discloses a CAD (computer aided design) data creation method that can provide a CAD data file or a print screen for small-scale to large-scale design structures. The CAD data file creation method involves processing for converting the file format of design data created by spreadsheet software into another specific file format.
Further, Japanese Unexamined Patent Application Publication No. 2002-117147 discloses a coordinated system that can eliminate complimentary processing, such as information use-limitation and re-entry, that results from different specifications of information in computer databases at an application software level. This coordinated system includes processing for causing an extraction program to extract necessary data from a database, processing for inputting the extracted data to a recording medium or the like, and executing input of the extracted data to a recording medium or the like by using a CSV (comma separated value) compliant format.
Japanese Unexamined Patent Application Publication No. 10-154168 discloses a component automatic registration apparatus and method. In this technology, component catalog data and design specifications are standardized and compiled into a database, data entry is simplified to accomplish laborsaving in creation of a component library, and a CAD system is used to improve work efficiency in printed-circuit-board design. In such a registration apparatus and method, component automatic generator software automatically creates the component library based on various data, such as component outer-shape data, as data regarding a component mounted to a substrate corresponding to an input specification on a component library creation process.
In response to frequent design changes, Japanese Unexamined Patent Application Publication No. 11-39356 discloses a design data management method and an apparatus therefor that maintains coherence of design data, extracts change difference data, stores change history data, and soon. In order to associate data used by various applications in the system, when a data change occurs, the design data management method and the apparatus therefor include processing, such as checking data coherence, extracting difference data before and after change, and storing the change difference data. Further, data managed by designers/engineers and designing/engineering departments that are connected through a network are shared to achieve coordinated design-work environment.
For designing FPGAs, large-scale FPGAs are increasingly used as alternatives to conventional ASICs (application specified ICs) and the number of pins currently ranges from 500 to 1500. Due to the large number of pins, lead-time mistakes and design load have increased. Especially, for the data management, since the formats of pin layout materials are not unified and no link is available between the design data, it is difficult to manage the data. For library creation, it takes time to create a library of symbols of the FPGA with the large number of pins and the created library requires time-consuming comparison with pin names in logic design. Further, for feedback of a change, a large number of work hours is required to feed back a mount requirement and a pin layout change due to logic modification to the library, circuit, and mount process. Neither such problems associated with FPGA design nor means for solving the problems are not disclosed or suggested in Japanese Unexamined Patent Application Publication Nos. 11-110435, 8-44782, 2002-230052, 2002-117147, 10-154168, and 11-39356.